A Novel Architecture for Current-steering Digital to Analog Converters

This paper presents a novel Current Steering Digital to Analog Converter architecture to reduce area as well as power dissipation. The current cells of conventional binary weighted architecture require larger size of transistors for MSBs. In this paper, same sized current cell transistors for MSBs as that of LSBs and a current mirror circuit is used between the load and MSBs to provide necessary higher current. Here, 6-bit CSDAC is simulated. The area of this proposed CS-DAC has decreased by about 12% and power dissipation by about 50% in comparison with a conventional Binary architecture. Keywords—data converters, digital-to-analog, current steering, current mirroring,cascode I. Digital to analog converters required by digital signal processors, medical instruments, wireless communication and other various processing equipment has proved to be a continuous challenge for the analog designers to improve and develop new DAC architectures. Current steering DAC is most popular due to its high speed, high resolution and small size [1,2,3]. The basic block diagram of Current Steering DAC(CS-DAC) is shown in Fig.1. Figure 1 Block Diagram of Basic Current Steering DAC It has (2-1)current source transistors with cascode circuits and switching transistors. Static and dynamic performances of current-steering DACs are mostly determined by the accuracy of the current sources, Non-infinite output impedance and switching time. The current cells with cascaded topologies as shown in Fig.2, are satisfactory for static and dynamic output impedance requirements [2] [3]. Figure 2 Current cell with cascode transistor and switching transistor In this paper, design of a 6-bit Current Steering DAC has been reported. The technology used for the design is 180nm CMOS process. Larger sizes of current cell transistors at MSBs are avoided in this architecture by using Current mirror circuit. The paper is organized as follows. A review of the conventional architecture in given section II, the proposed architecture and its design considerations is described in section III. Simulation results are given in section IV followed by the conclusions in section V